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Dr. P. Nagarajan

Associate Professor

Department of Electronics & Communication Engineering

Contact Information

Email : nagarajp@srmist.edu.in


Ph.D Degree – PhD
Area or Subject – VLSI Design, Advanced Communication systems Applications
University – Anna University, Chennai
Awarded Year – March 2015

PG Degree – M.E
Area or Subject – Applied Electronics
University – Anna University, Chennai
Awarded Year – June 2009

UG Degree – B.E
Area or Subject – Electronics and Communication Engineering
University – Anna University, Chennai
Awarded Year – May 2007

  • VLSI Design
  • Mixed-signal VLSI Design
  • Digital signal processing
  • Signals and systems
  • Electromagnetic fields
  • Electromagnetic interference and compatibility
  • Transmission lines and waveguides
  • Mobile and wireless communication
  • Electronic devices and circuits
  • ASIC Design
  • CMOS VLSI Design
  • CAD VLSI
  • Testing of VLSI circuits

  • VLSI Design – Circuits and system modeling (Analog / Digital / Mixed signal VLSI)
  • Image & signal Processing – FPGA Implementation, Bio medical images, Hyper Spectral Images

  • Nagarajan P,Renuka.M, Manikannan A and Dhanasekaran S, “Design and Simulation of a Novel 16T SRAM Cell for Low Power Memory Architecture ”Journal of Circuits, Systems and Computers, ISSN (print): 0218-1266
    |ISSN (online): 1793-6454, Impact Factor: 1.5,
    https://doi.org/10.1142/S0218126624500038 , June 2023. (SCI indexed).
  • Pandian Nagarajan, Thandapani Kavitha, Nagarajan Ashok Kumar, Alexander Shirly Edward, “POWER ENERGY AND POWER AREA PRODUCT SIMULATION ANALYSIS OF MASTER-SLAVE FLIP-FLOP. (2023). REVUE ROUMAINE DES SCIENCES TECHNIQUES — SÉRIE ÉLECTROTECHNIQUE ET ÉNERGÉTIQUE, ISSN (online): 00354066, Impact Factor: 0.7, https://doi.org/10.59277/RRST- EE.2023.4.19 , December 2023. (SCI indexed)
  • Nagarajan P, Ashokkumar N and VenkatRamana P, “Design of implicit pulsed – dual edge triggering flip flop for low power and high speed clocking systems”, International Journal of Wavelets, Multiresolution and Information Processing (IJWMIP), ISSN (print): 0377-2063, ISSN (online): 1793-690X, Impact Factor:1.276, Vol.17, No. 2,June2019,PP.1941009_1-1941009_19 1941009 (19 pages) (SCI indexed)
  • Nagarajan, P., Manoharadas, S., Dhasarathan, V. et al, “Cancer Detection Using Multi-layered Kretschmann Configuration–based Refractive Index Sensor”, Plasmonics, ISSN (online): 1557-1955, Impact Factor: 3.3, https://doi.org/10.1007/s11468-024-02381-7 , June 2024 , (SCI indexed)
  • Nagarajan P, Jacob Wekalao ,· Ashokkumar N, Shobhit K. Patel, “Design and Analysis of a Plasmonic MetasurfaceBased Graphene Sensor for Highly Sensitive and LabelFree Detection of COVID19 Biomarkers”, Plasmonics, ISSN (online): 1557-1955, Impact Factor: 3.3,July 2024, (SCI indexed).
  • P.Maniraj Kaumar , Nagarajan P, A.KaleelRahuman and T.Gobinath, “A Fuzzy Congestion Control in Wireless Sensor Networks based on Spider Monkey Optimization Algorithm”, IETE Journal of Research , ISSN (print): 0219-6913, ISSN (online): 0974-780Xs, Impact Factor:1.5, Vol.69, No.11,May2024,(SCIindexed).https://doi.org/10.1080/03772063.2024.2310123
  • P.Maniraj Kaumar , Nagarajan P, K. Ramamoorthy and S. Karthikeyan, “Spectrum Sensing and Resource Allocation for Frequency Hopping Based CRN Using Hazelnut Tree Search Algorithm”, IETE Journal of Research , ISSN (print): 0219-6913, ISSN (online): 0974-780Xs, Impact Factor:1.5, Vol.70,No.10,Dec2024,(SCIindexed).https://doi.org/10.1080/03772063.2024.2412148
  • N Ashokkumar , P Nagarajan, and P Venkat Ramana , “Quad-Rail Sense- Amplifier Based Network-On-Chip Router Design”, Journal of Computationaland Theoretical Nanoscience, American scientific publishers, ISSN: 1546- 1955 (Print): EISSN: 1546-1963 (Online), Vol 15, November/December 2018, PP. 3598–3600 (scopus).
  • P.Nagarajan , T.Kavitha and P Venkat Ramana, “Design and Evaluation of Power Efficient Shift Register Featuring Low Power Automatic Manufacturing Systems” Solid State Technology, ISSN: 0038-111X, Vol.63, Issue 5 ,2020. (Scopus).
  • P Nagarajan, I.Chandra, N Ashokkumar and M.Thiruveni, “Digital CMOS VLSI Implementation and Assessment of Power Efficient Delay Flip-Flop Using Dynamic CMOS Logic for Low Power VLSI Systems” published in IEEEXplore, DOI:10.1109/ICOSEC61587.2024.10722648 Publisher: IEEE, October 2024, pp.1019-1023 (Scopus).
  • P Nagarajan, , N Ashokkumar Kavitha Thandapan and B.Manimaran “CMOS VLSI Implementation of Implicit Pulsed Dual Edge Triggered Flip Flop using Pass Transistor Logic for Power Efficient Applications” published in IEEEXplore, DOI:10.1109/ICPCSN62568.2024.00170 Publisher: IEEE, July 2024, pp.319-324 (Scopus).
  • P Nagarajan, Kavitha Thandapani, N Ashokkumar, C Kanmani Pappa, “Design and Analysis of Charge Pumping Circuit for Low Power Charge Pump Based Phase Locked Loop Organization” published in IEEEXplore, DOI: 10.1109/ICOSEC58147.2023.10275837, Publisher: IEEE, 20-22 September 2023, pp.01-05 (Scopus).
  • P Nagarajan, N Ashok Kumar, Joshuva Arockia Dhanraj, T Senthil Kumar, “Delay Flip Flop based Phase Frequency Detector for Power Efficient Phase
    Locked Loop Architecture” published in IEEEXplore, DOI: 10.1109/ICEARS53579.2022.9752249, Publisher: IEEE, 13 April 2022,
    pp.410-414 (Scopus).
  • P Nagarajan, N Ashok Kumar, M. Krishnamurthy; Kavitha V P, “VLSI Architecture of Time-Mode Pulse Width Modulation First Order Low-Pass Filter” published in IEEE Xplore, DOI: 10.1109/ICCEBS58601.2023.10449278 ,Publisher: IEEE, 19 March 2024., pp.410-414 (Scopus).
  • P Nagarajan, N Ashok Kumar, P.Kabilamani; B. Manimaran, “FPGA Implementation of Image Registration Using Accelerated CNN” published in IEEE Xplore, DOI: 10.1109/ICCEBS58601.2023.10448526 , Publisher: IEEE, 19 March 2024., pp.410-414 (Scopus).
  • P Nagarajan, N Ashok Kumar, P.Kabilamani; B. Manimaran, “VLSI Implementation of an Efficient Lossless EEG Compression for WBAN Application” published in IEEE Xplore, DOI: 10.1109/ICCEBS58601.2023.10448571, Publisher: IEEE, 19 March 2024., pp.410-414 (Scopus).
  • N Ashok Kumar , P Nagarajan, Kavitha Thandapani, P.Kabilamani; B. Manimaran, “Reconfigurable Computer Architecture for Signal Processing Applications”published in IEEE Xplore, DOI: 10.1109/ICCEBS58601.2023.10449177, Publisher: IEEE, 19 March 2024., pp.410-414 (Scopus).
  • N Ashok Kumar, P Nagarajan, Joshuva Arockia Dhanraj, T Senthil Kumar, “Analysis of Millimeter-Wave based on Multichannel Wireless Networks- on-Chip” published in IEEEXplore, DOI: 10.1109/ICEARS53579.2022.9752077, Publisher: IEEE, 13 April 2022, pp.405-409 (Scopus).
  • C Venkataramanan; P Nagarajan; N Ashok Kumar; K.P Porkodi, “Design of Microstrip Patch Antenna with S-Slits for Wireless Applications”published in IEEEXplore, DOI: 10.1109/ICOSEC61587.2024.10722146, Publisher: IEEE, October 2024, (Scopus).
  • P. Kabilamani,K.P Porkodir,P Nagarajan; N Ashok Kumar,” Novel Framework Design of MIMO Antenna for 5G Applications”, published in IEEEXplore, DOI: 10.1109/ICOSEC61587.2024.107226646, Publisher: IEEE, October 2024, (Scopus).
  • R. Bhairavi; M. Thiruveni; Anita Christaline J; N. Ashokkumar; P. Nagarajan’”Improved Energy Balancing based Data Forwarding incorporating Whale optimization Technique in Underwater Acoustic Sensor Network” published in IEEEXplore, DOI: 10.1109/ICEEICT61591.2024.10718405, Publisher: IEEE, October 2024, (Scopus).
  • L Moha Sundari, T Senthil Kumar, P Nagarajan, UNVP Rajendranath, Ngangbam Phalguni Singh,” ICLM: Empirical Evaluation of Rheumatoid Arthritis Disorder using Image Classification and Linear Mapping Principles” published in IEEEXplore, DOI:
    10.1109/ICEARS53579.2022.9752400, Publisher: IEEE, 13 April 2022, pp.1120-
    1126 (Scopus)
  • P. Nagarajan, P Venkatramana, Shaik Javid Basha , “Design of Three-valued Logic Half-Subtractor using GNRFET” published in IEEExplore, DOI: 10.1109/RAEEUCCI57140.2023.10134349 , Publisher: IEEE, 30 May 2023, (Scopus).
    P. Nagarajan, P Venkatramana, Shaik Javid Basha , “Design of SB- GNRFET and D-GNRFET using QuantumATK” published in IEEExplore, DOI: 10.1109/ICNWC57852.2023.10127562, Publisher: IEEE, 25 May 2023, (Scopus).
  • P. Nagarajan, Kavitha Thandapani, C.Kanmani pappa, and N Ashok kumar, “MEMS Sensor Based V2V Communication Using Li-Fi Technology” publishedin IEEExplore, DOI: 10.1109/ICACCS57279.2023.10112879, Publisher: IEEE, 5 May 2023, (Scopus).
  • P. Nagarajan, C.Kanmani pappa , N Ashok kumar and Kavitha Thandapani, “Bluetooth based Garage Door Opening System” published in IEEExplore, DOI: 10.1109/ICSSIT55814.2023.10061046, Publisher: IEEE, 14 March 2023, (Scopus).
  • P. Nagarajan, R.Rama Devi, T.Kowsalya and D.Sathish Kumar “Health Care Assistive System in Hospital for Doctor to View the Patient’s Parameter in a Cloud Database using Light Fidelity” published in IEEExplore, DOI: 10.1109/I-SMAC55078.2022.9987390, Publisher: IEEE, 22 December2022, (Scopus).
  • P Nagarajan, R Ramadevi, D Lakshmi, T Kowsalya, S Jensie Anita “Foetal ultrasonographic sparse representation evaluation of spectral trust maps” publishedin AIP Conference Proceedings, https://doi.org/10.1063/5.0110574, Publisher: AIP, 30 January 2023, (Scopus).
  • N Ashokkumar , P Nagarajan, and P Venkat Ramana , “ NoC : A Frame Work for 2-dimensional and 3-dimentional architectures”, journal of advancedresearch in dynamical and control systems, JARDCS , ISSN :1943- 023X, Vol.9, Issue 14,April 2017, PP.2686-2694 ( Elsevier Scopus).
  • P.Nagarajan , T.Kavitha and S.Shiyamala ,“Efficient timing element design featuring low power vlsi application” International Journal of Engineering andTechnology (IJET), ISSN (Online) : 0975-4024, Vol 8 No 4, Aug-Sep 2016, PP. 1696-1705 (scopus).
  • P.Nagarajan , T.Kavitha and A.Arulmary, “Radio over fiber on gigabit passive optical network using QPSK modulation scheme” Journal of Optical Communications (JOC), ISSN: 2191-6322, Published online: 30 Nov 2020. (Elsevier Scopus).
    P.Nagarajan , T.Kavitha and S. Shiyamala, “FPGA implementation of arbiters algorithm for network-on-chip” ARPN Journal of Engineering and Applied Sciences, ISSN 1819-6608, Published online: VOL. 11, NO. 19, OCTOBER 2016. (Elsevier Scopus).
  • C.S. Anita, P. Nagarajan and G. Aditya Sairam, “Fake Job Detection and Analysis Using Machine Learning and Deep Learning Algorithms” , REVISTA GEINTEC-GESTAO INOVACAO E TECNOLOGIAS, ISSN : 2237-0722 , Vol. 11 No. 2 (2021), June 2021, PP. 642-650 ( Web of science , ESCI )
  • C.S. Anita, P. Nagarajan , E. Lakshminarayanan and M. Naveen Sankar, “Machine Vision and Machine Learning based Fruit Quality Monitoring”, REVISTA GEINTEC-GESTAO INOVACAO E TECNOLOGIAS, ISSN : 2237-0722 , Vol. 11 No. 2 (2021), June 2021, PP. 836-842 ( Web of science , ESCI )
  • P.Nagarajan , S.GowdhamKumar, Dr. R.M.Sekar, and Dr.S.Sivaranjani, “ Digital Design Systems Controlling Using FPGA Realization” Annals of R.S.C.B, ISSN1583-6258, , Vol. 25, Issue 5, 2021, PP. 570-582 . (Elsevier Scopus).
  • P.Nagarajan , S.GowdhamKumar, Dr. R.M.Sekar, and Dr.S.Sivaranjani, “A study on Strategies of Trading the News Using Massive Data Mining” , publishedin IEEEXplore, DOI: 10.1109/CCICT53244.2021.00029, Publisher: IEEE Xplore, 24 August 2021 (Scopus)
  • Gabariyala Sabadini C, P. Maniraj Kumar & P.Nagarajan “Design And Analysis Of Double Edge Triggered Clocked Latch For Low Power VLSI Applications” published in IEEE
    Xplore , DOI: 10.1109/ISCO.2016.7727012, Publisher:
    IEEE, 03 November 2016, (Scopus).
  • P.Nagarajan, R.Saravanan and P.Thirumurugan 2014 “Design of register element for low power clocking system”, Information-An International Interdisciplinary Journal, ISSN 1343-4500(print), ISSN 1344- 8994(electronic)Vol.17, no.6(B), pp.2903-2913, July 2014 (Annexure I – Impact Factor: 0.36)(Scopus)
  • Vithyalakshmi.N1, Nagarajan.P, Ashok Kumar.N, Vinoth.G.S, “Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review” International Journal of Engineering & Technogy, ISSN: 2227-524XVolume 7(3.1), 2018, 34-38, (Scopus)
  • Arthi C K and Nagarajan P 2015 “Design Of Sequential Elements For Low Power VLSI Applications”, International Journal of Applied Engineering Research ISSN 0973-4562 Vol. 10 No.5 (2015) pp. 4872-4876,(Annexure II)(Scopus).
  • T. Kavitha, S. Shiyamala & P. Nagarajan, ‘FPGA implementation of arbiters algorithm for network-on-chip’ ARPN Journal of Engineering and Applied Sciences, ISSN 1819-6608, VOL. 11, NO. 19, October 2016, PP.11451-11456(Scopus).
  • Dr. S. Shiyamala, Dr. T. Kavitha & Dr. P. Nagarajan, “Real time motion detection and tracking system by Kalman filter”, Journal of Theoretical and Applied Information Technology, ISSN: 1992-8645, Vol.95, No.16, 31st August 2017, PP .3851-3860 (Scopus).
  • P. Jeya Priyanka, Dr. K. Batri and Dr.P.Nagarajan, “Design and Analysis of Explicit Pulsed Register Element for Low Power VLSI Circuits”, Advances in Natural and Applied Sciences (ANAS), ISSN: 1995-0772, Special 9(17): 2015, PP.136-144.(Scopus)
  • Palagiri Avaneesh , Dr. P.Nagarajan, “Design and Functional Verification ofDDR SDRAM Controller to Access Multiple Banks”, Journal of Emerging Technologies and Innovative Research (JETIR), ISSN: 2349-5162, Volume 5, Issue 5 May 2018. PP.52-58 (UGC Listed)
  • Ellasamudram Durga , Dr. P.Nagarajan, “A Novel Design of Low Power and Area Efficient Line Decoder”, Journal of Emerging Technologies and Innovative Research (JETIR), ISSN: 2349-5162, Volume 6, Issue 6 June 2019. PP.593-600 (UGC Listed)
  • P.Nagarajan and R.Saravanan 2013 “Design and Analysis of Register Element for Low Power Clocking System” ,International Journal of ComputerScience and Mobile Computing, ISSN 2320–088X, Vol. 2, Issue 4,pp.38-45. (UGC Listed)
  • P.Nagarajan and P.Jenifer Martina 2013 “Hand Gesture Recognition Based Real-time Command System” ,International Journal of Computer Science and Mobile Computing, ISSN 2320–088X, Vol. 2, Issue 4,pp.295-299. (UGC Listed)
  • M. Guru Santhana Bharathi and P.Nagarajan 2014 “Design of Storage Element for Low Power VLSI System”, IJISET – International Journal of Innovative Science, Engineering & Technology, ISSN 2348 – 7968, Vol. 1 Issue 3. (UGC Listed)
  • P.Nagarajan and K.Nithya 2014 “Power Efficient Design of BILBO usingVarious Sequential Elements for Low power VLSI Applications (Basic5T-transistor and 5T- with MTCMOS)”, International Journal of Engineering Sciences & Research Technology. ISSN: 2277-9655 pp.835- 841( Impact Factor : 1.852)
  • S.Meena and P.Nagarajan 2014 “Power Efficient Design of Bilbo by Using Various Clocked Latches”, International Journal of Innovative Research in Science, Engineering and Technology, ISSN: 2319 – 8753, Volume 3, SpecialIssue 3, pp.1427-1434.
  • Gabariyala Sabadini C, Dr. P. Maniraj Kumar & Dr. P.Nagarajan “Design And Analysis Of Implicit Pulsed Double Edge Triggered Clocked Latch For Low Power Applications”, International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE), ISSN: 2278-909X Volume 4, Issue 11, November 2015. pp.2672 – 2678.
  • P.Jothimani and Dr.P.Nagarajan, “Smart Vehicle System Design For Road Condition And Detection Of Potholes And Humps On Road To Aid Drivers”, International Journal of Advanced and Innovative Research (2278-7844) / # 105 / Volume 4 Issue 11, 2015 ,pp.105-108.

  • P Nagarajan, Kavitha Thandapani, N Ashokkumar, C Kanmani Pappa, “Design and Analysis of Charge Pumping Circuit for Low Power Charge Pump Based Phase Locked Loop Organization” published in IEEEXplore, DOI: 10.1109/ICOSEC58147.2023.10275837, Publisher: IEEE, 20-22 September 2023, pp.01-05. 4th International Conference on Smart Electronics and Communication (ICOSEC).
  • P. Nagarajan, N. Ashok Kumar, and Joshuva Arockia Dhanraj, “ Delay Flip Flop-based Phase Frequency Detector for Power Efficient Phase Locked Loop Architecture,” published in IEEE Xplore, DOI: 10.1109/ISCO.2016.7727012, Publisher: IEEE, March3, 2022, International Conference on Electronics and Renewable Systems (ICEARS)
  • N. Ashok Kumar, P. Nagarajan, Joshuva Arockia Dhanraj, and T. Senthil Kumar, “ Analysis of Millimetre-Wave based on Multichannel Wireless Networks-on-Chip,” published in IEEE Xplore, DOI: 10.1109/ICEARS53579.2022.9752077 , Publisher: IEEE, March 2022, International Conference on Electronics and Renewable Systems (ICEARS)
  • P. Nagarajan, “Low-power VLSI design approaches for CMOS and CNTFET-based circuit design,” International Conference on Recent Trends in Information, Communication and Pervasive Technologies (ICRTICPT-2022), May 2022, Tamil Nadu, India
  • P. Nagarajan, “Design and Evaluation of single edge triggering flip flops using split path techniques for low power VLSI architectures,” International Conference on Recent Trends in Information, Communication and Pervasive Technologies (ICRTICPT-2022), May 2022, Tamil Nadu, India
  • P. Nagarajan, P. Venkatramana, and Shaik Javid Basha , “Design of a Three-Valued Logic Half-Subtractor Using GNRFET,” International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI), May30, 2023
  • P. Nagarajan, P. Venkatramana, and Shaik Javid Basha , “Design of SB-GNRFET and D-GNRFET using Quantum ATK,” International Conference on Networking and Communications (ICNWC), May25, 2023
  • P. Nagarajan, Kavitha Thandapani, C. Kanmani Pappa, and N. Ashok Kumar, “MEMS Sensor-Based V2V Communication Using Li-Fi Technology,” International Conference on Advanced Computing and Communication Systems (ICACCS), May5, 2023
  • P. Nagarajan, C. Kanmani Pappa, N. Ashok Kumar, and Kavitha Thandapani, “Bluetooth-based Garage Door Opening System,” 5th International Conference on Smart Systems and Inventive Technology (ICSSIT), March14, 2023
  • P. Nagarajan, R. Rama Devi, T. Kowsalya and D. Sathish Kumar, “Health Care Assistive System in Hospital for Doctor to View the Patient’s Parameter in a Cloud Database using Light, Sixth International Conference on I-SMAC (IoT in Social, Mobile, Analytics and Cloud) (I-SMAC), December 2022
  • P. Nagarajan, R. Ramadevi, D. Lakshmi, T. Kowsalya, and S. Jensie Anita, “Foetal ultrasonographic sparse representation evaluation of spectral trust maps,” Recent Advancements in Mechanical Engineering and Industrial Management, June 2021
  • P. Nagarajan, “Investigating Wireless Optical Communication Systems for Inter-Satellite Communication Using QPSK Modulation Technique,” International Conference on Data Intelligence and Cognitive Informatics (ICDICI-2019), July 2021, Tamil Nadu, India
  • P. Nagarajan, R. Saravanan, “Power-efficient design of storage elements for low power VLSI International Conference on Recent Innovations in Engineering (ICRIE 2014), Tamil Nadu, India
  • P. Nagarajan, “Design and functional verification of a DDRSDRAM controller to access multiple banks,” International Conference on Electrical, electronics and Communication Engineering (ICEECE-2018), Hyderabad, India
  • N. Ashok Kumar, P. Nagarajan, “3D Router Communication Based on Chip Topology,” International Conference on Innovation in Science and Engineering Research (ICISER’18), March 2018, Chennai, India
  • N. Ashok Kumar, P. Nagarajan, “3D Wired and Wireless Network on Chip NoC,” International Conference on Inventive Communication and Computational Technologies (ICICCT’19), April 2019, Namakkal, India
  • N. Ashokkumar, P. Nagarajan, “Design Challenges for 3-D Network-on-Chip (NoC)”, International Conference on Sustainable Communication Networks and Applications (ICSCN’19), July 2019, Erode, India
  • P. Nagarajan, “Review on Flip flops for Low Power and High Performance VLSI Clocking Systems,” International Conference on Applications of Mems, nano and Smart Materials (ICMNSM-2019), December 2019, Tiruapati, India
  • P. Nagarajan, “A Design and Evaluation of Parallel to Serial Data Converters Featuring Low Power Digital CMOS VLSI Systems,” International Conference on Applications of Mems, nano and Smart Materials (ICMNSM-2019), December 2019, Tiruapati, India
  • C. Gabariyala Sabadini, Dr. P. Maniraj Kumar, and Dr. P. Nagarajan, “Design and Analysis of Double Edge Triggered Clocked Latch for Low Power VLSI Applications,” 10th International Conference on Intelligent Systems and Control (ISCO), January 2016, DOI:10.1109/ISCO.2016.7727012 (published in IEEE Xplore on November 3, 2016)
  • S. Meena and P. Nagarajan (2014), “Power Efficient Design of Bilbo By Using Various Clocked Latches,” International Conference on Innovations in Engineering and Technology (ICIET’14), Madurai, India
  • M. Guru Santhana Bharathi, P. Nagarajan “ Power-efficient design of storage elements for low-power VLSI systems,” International Conference on Recent Innovations in Engineering (ICRIE 2014), Palani, India
  • P. Nagarajan, P. Jennifer Martina, “Hand Gesture Recognition Based Real-Time Command System,” International Conference on Innovation in Intelligent Instrumentation 2013, Optimisation and Signal Processing, Coimbatore, India
  • P. Nagarajan, “Performance Analysis of Broadband OFCDMA Systems,” National Conference on ESIC’09, Dindigul, India

Patents Published:

  • Title of the invention: DESIGN OF POWER GATED DOUBLE EDGE TERIGGERED FLIP FLOP USING SLEEP TRANSISTOR TECHNIQUE (PG- STDETFF), Application No.201741000167, Publication Date: 02/06/2017.  Field of Invention: Electronics. Patent No: 534840, Date of Grant: 25/04/2024.
  • Published TEN numbers of Intellectual Patents (Indian Patent) in VLSI CIRCUIT   MODELING & SYSTEM DESIGN AND BIOMEDICAL IMAGE PROCESSING.
  •  Title of the invention: DESIGN OF IMPLICIT PULSED -DOUBLE EDGE   TRIGGERED ELIP FLOP (IP-DETFF) FOR LOW POWER CLOCKING SYSTEM. Application No.201641042620  Publication Date: 02/06/2017
  • Title of the invention: DESIGN OF DOUBLE EDGE TRIGGERED MASTER SLAVE FLIP-FLOP USING A NOVEL PARALLEL SLEEPY STACK TECHNIQUE, Application No. 201741032973 A, Publication Date: 22/03/2019.
  • Title of the invention: A SIMPLE AND EFFECTIVE DEVICE FOR DETECTION AND DIAGNOSING THE EARLIAR DIABETES THYROID UBNORMAL, Application No. 201941013976 A, Publication Date: 17/05/2019.
  • Title of the invention: “DESIGN OF RISING EDGE TRIGGERING FLIP FLOP USING PSEUDO-NMOS TECHNIQUE FOR LOW POWER CLOCKING SYSTEM”. Application No. 201941048075, Publication Date: 28/05/2021.
  • Title of the invention: “HYBRID STORAGE ARCHITECTURE FOR IoT”, Application No. 202241033343, Publication Date: 17/06/2022.
  • Title of the invention: “MACHINE LEARNING BASED TECHNIQUE INTEGRATED WITH SIX SIGMA METHODOLOGIES FOR PREDICTING THE STRESS OF EMPLOYEES IN AN ORGANIZATIOIN”, Application No. 202241057567, Publication Date: 07/10/2022.
  • Title of the invention: “MEDICAL WASTE TREATMENT DEVICE”, Application No. 383823-001, Publication Date: 13/04/2023.
  • Title of the invention: “IOT-DRIVEN REAL-TIME STRUCTURAL HEALTH MONITORING AND DAMAGE IDENTIFICATION USING AI Application No. 202341026223 A, Publication Date: 05/05/2023.

Patents Registered:

  • Title of the invention: “Three Dimensional (3D 4X4X3) Social Based Network on Chip Architecture (NoC)”. Application No. 201841000052, CBR No. 20.

  • Published a Book titled “VLSI Design “in SCHOLAR’S PRESS publication, Print ISBN: 978-620-5-52397-1, https://images.our-assets.com/fullcover/2000x/9786205523971.jpg, July 2023.
  • Published a book titled “VLSI Design “in SCHOLAR’S PRESS publication, print ISBN:978-620-5-52397-1, https://images.our assets.com/fullcover/2000x/9786205523971.jpg, July 2023.
  • Published a book titled “Advanced Digital System Design “in SCHOLAR’S PRESS publication, ISBN: 978-613-8-91046-6, December 2022.
  • Published a book titled “Advanced Embedded System Design “in LAP Lambert Academic Publishing, ISBN 978-3-030-03145-9, ISBN-13:978-6200117625, ISBN-10:6200117624, July5, 2021
  • Published a book chapter named “Low Power Design Methodology “ in the book titled “Very-Large-Scale Integration“ in INTECH OPEN publication, ISBN: 978-3-030-03145-9, print ISBN: 978-3-030-03146-6, DOI: 10.5772/65525, February
  • I published lecture notes on “ Quad-Rail Sense-Amplifier-Based NoC Router Design “ in the book titled “Data Engineering and Communication Technologies“ in Springer publication, ISBN: 978-953-51-3864-8, print ISBN: 978-953-51-3863-1, DOI: 1007/978-3-030-03146-6, pp. 1449–1454, January 2019
  • Published a book chapter named “Design challenges for 3 Dimensional Network-on-Chip (NoC) “in the book titled “Sustainable Communication Networks and Applications in Springer publication, Online ISBN: 978-3- 030-34515-0, PrintISBN:978-3-030-34514-3, DOI: https://doi.org/10.1007/978-3-030-34515-0_82, November pp. 773–782
  • Published a book chapter named “3D (Dimensional): wired and wireless network-on-chip (NoC) “in the book titled “NETWORKS AND SYSTEMS” “in Springer publication, online ISBN: 978-981-15-0146-3, print ISBN: 978-981-15-0145-6, DOI: https://doi.org/10.1007/978-981-15- 0146-3_12, pp113-119, 30th January
  • I published lecture notes on “ Investigating Wireless Optical Communication Systems for Inter-Satellite Communication Using QPSK Modulation Technique“ in the book titled “Algorithms for Intelligent Systems” in Springer publication , ISBN: 978-981-16-6460-1 DOI: 10.1007/978-981-16-6460-1_66, pp. February1, 2022
  • P. Nagarajan, Kavitha T , Arul Mary, “Distributed optical fiber sensing systemfor leakage reduction in underground energy storage pipeline using Machine –learning techniques “ materials for sustainable energy storage at Nano Scale–  CRC PRESS, Taylor & Francis , June 2023.

  • Participated 4 day residential Workshop on “Design Thinking” Conducted by intellect School of Design Thinking Collaborated with SRMIST on June 2023. Venue : 8012 FinTech Design Center, Siruseri, Chennai.
  • Participated one day Awareness/ Training Program on “Intellectual Property Rights” Under National Intellectual Property Awareness Mission – NiPAM Conducted by intellectual Property Office, India on 26th October 2023.
  • Conducted a two-day national workshop for researchers on “VLSI architectures for biomedical image processing applications,” fully sponsored by CSIR
  • Organised a six-day AICTE-sponsored short-term training programme on “ Recent Trends Research Challenges on Nano CMOS VLSI Circuits by Industry Standard EDA Tools.”
  • Conducted a two-day seminar on “Transmission lines and waveguides with KETAB STUDIO V4.0.0 Lite.”
  • Conducted a two-day workshop on “Recent Research Tools for VLSI Design.” (Tanner, Microwind, Cadence)

  • Delivered guest lecture as resource person on “MOTIVATION OF STUDENTS TOWARDS CONVERSION OF PROJECT INTO PATENT” in the webinar conducted by IPR Cell at NPR College of engineering and technology, Dindigul, May 2023.
  • I delivered a guest lecture as a resource person on “MOTIVATION OF STUDENTS TOWARDS CONVERSION OF PROJECT INTO PATENT” in the webinar conducted by the IPR Cell at NPR College of Engineering and Technology, Dindigul, May 2023
  • Delivered a guest lecture as a resource person on “LOW POWER VLSI DESIGN METHODOLOGIES FOR CMOS AND CNTFET-BASED CIRCUITS AND SYSTEMS” for summer vacation 2020 at the SSM Institute of Engineering and Technology, Dindigul
  • I delivered a guest lecture as a resource person on “CARBON NANOTUBE FIELD EFFECT TRANSISTORS: FABRICATION AND APPLICATIONS” for 6 days of FDTP at Sree Vidyanikethan Engineering College, Tirupati, and Andhra Pradesh
  • I delivered a guest lecture as a resource person in the Anna University-approved faculty development training programme (FDTP) on “EMBEDDED AND REAL TIME SYSTEMS” titled “ POWER EFFICIENT METHODOLOGIES TO DESIGN LOW-POWER VLSI CIRCUITS FOR EMBEDDED REAL TIME SYSTEMS” for summer vacation 2022 at AMRITA Vishwa Vidyapeetham University, Bangalore
  • I delivered a guest lecture as a resource person in a national-level webinar on “Metal Oxide Semiconductor and Carbon Nano Tube Field Effect Transistors” through the Zoom platform in June 2020 at TDMNS College, Tamil Nadu
  • I delivered a guest lecture as a resource person in the Anna University-approved faculty development training programme (FDTP) on “VLSI DESIGN” for winter vacation 2016 at the SSM Institute of Engineering and Technology, Dindigul
  • I delivered a guest lecture as a resource person in the Anna University-approved faculty development training programme (FDTP) on “digital signal processing” for summer vacation 2017 at the SSM Institute of Engineering and Technology, Dindigul
  • I delivered a guest lecture as a resource person in the Anna University-approved faculty development training programme (FDTP) on “Electromagnetic Fields” for winter vacation 2017 at Adhi College of Engineering and Technology, Kanchipuram

  • Completed 8 Week online Certification course titled “Road Map for Patent Creation” Conducted by NPTEL – AICTE , Swayam with Consolidated score of 81% , Secured Elite in the duration of January-March 2023.
  • Completed 4 Week online Certification course titled “Design Thinking – A Primer” Conducted by NPTEL-AICTE, Swayam with Consolidated score of 75% , Secured Elite in the duration of July-August 2023.

  • Working as an Associate Professor at SRMIST, Vadapalani Campus, from January30
  • I worked as a professor at Rajalakshmi Institute of Technology, Chennai, from 05-10-20 to 27-01-23
  • I worked as an associate professor at Sree Vidyanikethan Engineering College. Tirupati from 17-07-17 to 04-10-20
  • From February19, 2016 to July14, 2017, I worked as an Associate Professor at VEL Tech University in Chennai.
  • I worked as a lecturer and assistant professor at PSNA College of Engineering and Technology, Dindigul, from May30 to February16
  • I worked as a teaching assistant at RVS College of Engineering and Technology, Dindigul, from May10, 2007 to May29, 2009

  • Recipient of the university rank holder for Master of Engineering in the year 2009 from Anna University
  • Major research Project titled “Design and Development of Optimized Miniature Antenna Modules with Duality Function for Inflantable Satellite Antenna Setup” funded by ISRO under the scheme of Respond is completed as CO-PI.  Project ID: OGP172, ISRO CODE: ISRO/RES/3/758. Sanctioned Amount: 33, 40,000.
  • Design and Development of On board Miniature satellite module is completed with various sensors payload to monitor the space environment.  It was launched on 18th November 2022 at ISRO-SRIHARIKOTA as one of the payloads in VIKRAM –S (INDIA’S first private launching Rocket developed by SKYROOT Space startup) into Sub orbital layer. (100 Kms above mean sea level – in Karman layer)
  • I obtained a medal and merit certificate (university rank holder) in Master of Engineering from Anna University, Tiruchirapalli
  • Secured Academic Topper awards in Bachelor of Engineering from OCET affiliated with Anna University, Chennai

  • Honorary Member: IRED, SNM10100059776, 2019
  • Life Member: SCIENCE AND ENGINEERING INSTITUTE, 20210811001, 2021
  • Life Member: IAENG 219786, 2018
  • Life Member: ISTE-LM 137429, 2023

Funded Projects and Research Activities

  • Major research Project titled “Design and Development of Optimized Miniature Antenna Modules with Duality Function for Inflantable Satellite Antenna Setup” funded by ISRO under the scheme of Respond is completed as CO-PI. Project ID: OGP172, ISRO CODE: ISRO/RES/3/758. Sanctioned Amount: 33, 40,000.
  • Design and development of The miniature satellite module is complete with various sensor payloads to monitor the space environment. It was launched on November 18, 2022, at ISRO-SRIHARIKOTA as one of the payloads in VIKRAM-S (India’s first private launch rocket developed by SKYROOT Space Startup) into the suborbital layer. (100 km above mean sea level, in the Karman layer)
  • Submitted funded project for TNSCST in the domain of Teaching and Learning Pedagogy for STEAM (Science, Technology, Engineering, Arts and Mathematics) Education Sector under the Research Funding Scheme
  • Applied funded project in the Ministry of Electronics and Information Technology (DST-SERB) under core research grant as principal investigator titled “Design of Optimised Charge Pump Phase Locked Loop Based Frequency Synthesiser for Advanced Communication Systems” in the domain of VLSI design
  • I received a grant of Rs. 50000 from CSIR (Council of Scientific and Industrial Research) to conduct the workshop for researchers in the domain of VLSI architectures for biomedical image processing applications
  • Guiding three Ph.D. scholars in the domain of VLSI design and RF circuit modelling under VELTECH University Chennai
  • Acting as a doctoral committee member for eight Ph.D. scholars pursuing Ph.D. under Anna University, Chennai

Work in progress

  • Preparing the research proposal in the domain of learner-centred teaching and learning pedagogy for the STEAM education sector and readily having to submit it to the right agency. (Research in Teaching and Learning Methodology)
  • I am preparing a research proposal titled “Design of an Optimised Charge Pump Phase Locked Loop Based Frequency Synthesiser for Advanced Communication Systems” in the domain of VLSI design. (VLSI-Core research work)  is ready for a funded project under the Start-Up Research Grant as Principal Investigator